Michael O’Sullivan

As exchanges push latency even lower—with 25G Ethernet, RF links, and photonics—many HFT firms are running into the limits of FPGA-based acceleration. Timing closure challenges, resource ceilings, and verification overhead are increasingly hard to ignore as they stretch the FPGA development cycle.

As discussed at recent STAC Summits, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions, but a shortage of experienced, skilled personnel causes painful lead times and uncomfortable prioritization decisions.

It's no secret that FPGAs are a favorite component for ultra-low latency system engineers. Firms can gain a significant edge by placing relatively simple trading strategies in an FPGA to avoid user space entirely.

A straightforward way to design low-latency hardware is by distributing the performance budget across the system's blocks. The design achieves its latency goals if the performance measured in each block meets its budget in all use cases.